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| SL74HC123 Dual Retriggerable Monostable Multivibrator The SL74HC123 is identical in pinout to the LS/ALS123. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. There are two trigger inputs, A INPUT (negative edge) and B INPUT (positive edge). These inputs are valid for rising/falling signals. The device may also be triggered by using the CLR input (positiveedge) because of the Schmitt-trigger input; after triggering the output maintains the MONOSTABLE state for the time period determined by the external resistor RX and capacitor CX. Taking CLR low breaks this MONOSTABLE STATE. If the next trigger pulse occurs during the MONOSTABLE period it makes the MONOSTABLE period longer. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 3.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC123N Plastic SL74HC123D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 16 =VCC PIN 8 = GND Note (1) CX, RX, DX are external components. (2) DX is a clamping diode. The external capacitor is charged to V in the stand-by CC state, i.e. no trigger. When the supply voltage is turned off CX is discharged mainly through an internal parasitic diode. If CX is sufficiently large and VCC decreases rapidy, there will be some possibility of damaging the I.C. with a surge current or latch-up. If the voltage supply filter capacitor is large enough and VCC decrease slowly, the surge current is automatically limited and damage the I.C. is avoided. The maximum forward current of the parasitic diode is approximately 20 mA. A Inputs B H X H L L X H X L L H L X CLR H H H H L* L * Outputs Q Q Note Output Enable H* H * Inhibit Inhibit Output Enable Output Enable Inhibit X = don't care * - except for monostable period SLS System Logic Semiconductor SL74HC123 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) A, B, CLR CX, RX Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 30 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time - CLR (Figure 2) A or B RX CX ** Min 3.0 0 -55 VCC =2.0 V VCC =4.5 V VCC =6.0 V 0 0 0 VCC <4.5 V VCC 4.5 V 10 2.0 0 ** Max 6.0 VCC +125 1000 500 400 No Limit 1000 1000 No Limit Unit V V C ns External Timing Resistor External Timing Capacitor k F The In74HC123 will function at 2.0 V but for optimum pulse width stability, V should be above CC 3.0 V. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC123 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol VIH Parameter Test Conditions V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 85 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 125 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 A V Unit V Minimum HighVOUT=0.1 V or VCC-0.1 V Level Input Voltage IOUT 20 A Maximum Low VOUT=0.1 V or VCC-0.1 V Level Input Voltage IOUT 20 A Minimum HighLevel Output Voltage VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA VIL V VOH V VOL Maximum LowLevel Output Voltage VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA IIN Maximum Input Leakage Current (A, B, CLR) Maximum Input Leakage Current (RX, CX) Maximum Quiescent Supply Current (per Package) Standby State VIN=VCC or GND IIN VIN=VCC or GND 6.0 50 500 500 nA ICC VIN=VCC or GND Q1 and Q2 = Low IOUT=0A 6.0 130 220 350 A 25C -45C to 85C 600 -55C to 125C 800 A ICC Maximum Supply Current (per Package) Active State VIN=VCC or GND Q1 and Q2 = High IOUT=0A Pins 15 and 7 = 0.5 VCC 6.0 400 SLS System Logic Semiconductor SL74HC123 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Input A or B to Q or Q (Figures 1 and 3) Maximum Propagation Delay , CLR to Q or Q (Figures 2 and 3) Maximum Output Transition Time, Any Output(Figures 2 and 3) Maximum Input Capacitance A, B, CLR CX, RX V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 255 50 45 215 45 35 75 16 14 10 25 85 C 320 65 55 270 55 45 95 20 17 10 25 125 C 385 75 65 325 65 55 110 22 20 10 25 Unit ns tPLH, t PHL ns tTLH, t THL ns CIN pF Power Dissipation Capacitance (Per Multivibrator) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Typical @25C,VCC=5.0 V 150 pF TIMING REQUIREMENTS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol trec Parameter Minimum Recovery Time, Inactive to A or B (Figure 2) Minimum Pulse Width, Input A or B (Figure 1) Minimum Pulse Width, CLR (Figure 2) Maximum Input Rise and Fall Times, CLR (Figure 2) A or B (Figure 2) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 25 C to -55C 0 0 0 100 20 17 100 20 17 1000 500 400 Guaranteed Limit 85C 0 0 0 125 25 20 125 25 20 1000 500 400 No Limit 125C 0 0 0 150 30 25 150 30 25 1000 500 400 Unit ns tw ns tw ns tr, tr ns SLS System Logic Semiconductor SL74HC123 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Test Circuit SLS System Logic Semiconductor SL74HC123 TIMING DIAGRAM EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor |
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